1. Field of the Invention
The invention relates to a delay line circuit, and more particularly to a delay line circuit for a system-on-chip.
2. Description of the Related Art
In a system-one-chip, there are a large number of circuits which are used to process the phase relationship between signals. Multi-bit digital coding is required to control the phase relationship. A delay line circuit can be applied to achieve this function. For example, a delay line circuit can be controlled by 7-bit digital coding, so as to achieve delay adjustment by increasing 0˜127 delay steps for an input signal. Thus, the phase relationship between an output signal and a reference signal can be controlled.
FIG. 1 shows a conventional delay line circuit 10. The delay line circuit 10 comprises a fine delay unit FD, coarse delay units CD1˜CD31, a dummy coarse delay unit DCD, and switches SW0˜SW31. There are four sets of codes of a control signal inputted to the fine delay unit FD. Switch control signals C0˜C31 are used to control the thirty-two (32) switches SW0˜SW31 to be turned on or off. Only one switch is turned on every time. Accordingly, 128 coding values formed by seven (7) bits are represented by four (4) multiplied by 32 (4×32). The delay of the coarse delay units CDN are equal and 4 times the delay step of the fine delay unit FD.
FIG. 2 shows the circuit of the fine delay unit FD. The fine delay unit FD comprises P-type metal oxide semiconductor (PMOS) transistors P1˜P10 and N-type metal oxide semiconductor (NMOS) transistors N1˜N10 which are coupled in the connection shown in FIG. 2. The PMOS transistor P9 and the NMOS transistor N9 are coupled together as an inverter. The PMOS transistors P1˜P4 are coupled in parallel between the source of the PMOS transistor P9 and a power voltage DVDD. The gate of the PMOS transistor P1 is coupled to a ground voltage DVSS. The gates of the PMOS transistors P2˜P4 are coupled to control signals SP0˜SP2 respectively. The NMOS transistors N1˜N4 are coupled in parallel between the source of the NMOS transistor N9 and the ground voltage DVSS. The gate of the NMOS transistor N1 is coupled to the power voltage DVDD. The gates of the NMOS transistors N2˜N4 are coupled to control signals SN0˜SN2 respectively. For example, when the control signal SP0 is 0, the control signal SN0 is 1; when the control signal SP1 is 1, the control signal SN1 is 0. The connection of the PMOS transistors P5˜P8 is the same as the aforementioned connection of the PMOS transistors P1˜P4, while the connection of the NMOS transistors N5˜N8 is the same as the above connection of the NMOS transistors N1˜N5, thus the related omitted description is omitted here. The fine delay unit FD achieves the delay change by controlling the PMOS transistors P2˜P4 and P6˜P8 and the NMOS transistors N2˜N4 and N6˜N8 to be turned on or off. For example, when the control signals SP0˜SP2 are 1 and the control signals SN0˜SN2 are 0, the delay of the fine delay circuit FD is minimum; when control signals SP0˜SP2 are 1 and the control signals SN0˜SN2 are 0, the delay of the fine delay circuit FD is maximum.
FIG. 3 shows the circuit of the coarse delay unit CD1. The circuit structures of the coarse delay units CD2˜CD31 are the same as those of the coarse delay unit CD1, thus the related description is omitted here. The coarse delay unit CD1 comprises PMOS transistors P11˜P14 and NMOS transistors N11˜N14. In the coarse delay unit CD1, the delay of the coarse delay unit CD1 changes to be four times the delay step of the fine delay unit FD by adjusting the respective sizes of the transistors.
Generally, in order to ensure the uniformity of the delay steps, a fine delay unit FD and thirty-one coarse delay units CD1˜CD31 are arranged by a straight line in the circuit layout, to guarantee that the loads of the delay units are equal. There are three critical factors for the uniformity of the delay steps. First, the delay steps of the fine delay unit FD are equal, which can be achieved by adjusting the sizes of the transistors in the fine delay unit FD repeatedly. FIG. 4 shows a partial circuit layout 40 of the fine delay unit FD in FIG. 2. In FIG. 4, a circuit layout a part of the transistors in the first-stage circuit of the fine delay unit FD (that is the PMOS transistors P1˜P4 and P9 and the NMOS transistors N1˜N4 and N9) is presented. The connection between the drains is not shown in FIG. 4. In order to ensure the accurate uniformity of the delay steps, the sizes of the PMOS transistors P1˜P4 are different. This circuit layout may make the parasitical capacitance of the drains of the PMOS transistors P1˜P4 to be larger. Second, the delay steps of the coarse delay units have to be precisely four times the delay step of the fine delay unit. The delay step of the fine delay unit changes by turning on or off the switch, while the delay steps of the coarse delay units are fixed absolute delay steps. Since the delay of the fine delay unit FD and the delays of the coarse delay units CDN are generated in different ways, the multiple relationships therebetween cannot be achieved accurately, particularly when different power voltages and temperatures are involved. Third. the fine delay unit FD and the coarse delay units CD1˜CD31 are arranged in a straight line in the circuit layout, however, this makes the circuit layouts of the internal module of the SOC complicated and wastes space, particularly, for 28 nm processes or advanced processes which require that polysilicons of all core transistors are arranged in the same direction. Thus, the flexibility of the layout of the delay line circuit is greatly reduced. In other words, different designs are required for different delay line circuits, which increases the cost.